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very high common - mode voltage precision difference amplifier data sheet ad8479 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 600 v common - mode voltage range rail - to - rail output fixed gain of 1 wide power supply range of 2.5 v to 18 v 55 0 a typical power supply current e xcellent ac specifications 90 db minimum cmrr 13 0 khz bandwidth high accuracy dc performance 5 ppm maximum gain nonlinearity 10 v/c maximum offset voltage drift 5 ppm/c maximum gain drift applications high voltage current sensing battery cell voltage monitor s power supply current monitor s motor control s isolation general description the ad8479 is a difference amplifier with a very high inpu t common - mode voltage range. the ad8479 is a precision device that allows the user to accurately measure differential signals in the presence of high common - mode voltages up to 60 0 v. the ad8479 can replace costly isolation amplifiers in applications that do not require galvanic isolation. t he device operates over a 60 0 v common - mode voltage range and has inputs that are protected from common - mode or diffe rential mode transients up to 6 00 v. the ad8479 has low offset voltage , low of fset voltage drift, low gain drift, low common - mode rejection drift, and excellent common - mode rejection ratio ( cmrr ) over a wide frequency range. the ad8479 is available in a space - saving 8 - lead soic package and is operational ove r the ?40c to +125c temperature range. functional block diagram 2 3 4 1 7 6 8 ref(?) ?in 1m? ad8479 1m? +in ?v s nc notes 1. nc = no connec t . do not connect t o this pin. +v s output 111 18-001 5 ref(+) figure 1 . ?800 ?600 ?400 ?200 0 200 400 600 800 ?20 ?15 ?10 ?5 0 5 10 15 20 common-mode vo lt age (v) v out (v) v s = 15 v v s = 5 v 111 18- 1 10 figure 2 . input c ommon - m ode voltage vs. output voltage
ad8479 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 11 applications information .............................................................. 12 basic connections ...................................................................... 12 single - supply operation ........................................................... 12 system - level decoupling and grou nding .............................. 12 using a large shunt resistor .................................................... 13 output filtering .......................................................................... 14 gai n of 60 differential amplifier ............................................. 14 error budget analysis example ............................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 4/1 3 revision 0: initial version
data s heet ad8479 rev. 0 | page 3 of 16 specifications v s = 15 v, ref (?) = ref (+) = 0 v, r l = 2 k?, t a = 25c , unless otherwise noted. table 1. a grade b grade parameter test condition s/comments min typ max min typ max unit gain v out = 10 v, r l = 2 k? nominal gain 1 1 v/v gain er ror 0.01 0.02 0.005 0.01 % gain nonlinearity 4 10 2 5 ppm gain drift t a = t min to t max 3 5 3 5 ppm/c offset voltage offset voltage v s = 15 v 0.5 3 0.5 1 mv v s = 5 v 0.5 3 0.5 1 mv offset voltage drift t a = t min to t max 3 15 3 10 v/c power supply rejection ratio (psrr) v s = 2. 5 v to 15 v 84 100 90 100 db inp ut common - mode rejection ratio (cmrr) v cm = 60 0 v dc t a = 25c 80 90 90 96 db t a = t min to t max 80 90 db v cm = 1200 v p - p, dc to 1 2 khz 80 80 db operating voltage range common - mode 600 600 v differential 14. 7 14.7 v input operating impedance common - mode 500 500 k? differential 2 2 m? output output voltage swing r l = 2 k? ?v s + 0.3 + v s ? 0.3 ?v s + 0 .3 +v s ? 0.3 v output short - circuit current 5 5 5 5 ma capacitive load stable operation 500 500 pf dynamic response small signal ? 3 db bandwidth 130 130 khz slew rate 7.5 8 7.5 8 v/s full power bandwidth v out = 20 v p -p 100 100 khz settling time 0.01%, v out = 10 v step 11 11 s 0.00 1%, v cm = 10 v step 15.4 15.4 s output voltage noise 0.01 hz to 10 hz 30 35 30 35 v p - p noise spectral density f 100 hz 1.6 1.6 v/hz power supply o perating voltage range 2.5 18 2.5 18 v supply current v out = 0 v 550 650 550 650 a t a = t min to t max 850 850 a temperature range specified performance t a = t min to t max ?40 + 85 ?40 + 85 c operational ?40 +125 ?40 +125 c
ad8479 data sheet rev. 0 | page 4 of 16 absolute maximum rat ings table 2. parameter rating supply voltage, v s 18 v input voltage range continuous 600 v common - mode and differential, 10 sec 900 v output short - circuit dur ation indefinite ref(?) and ref(+) ? v s ? 0.3 v to + v s + 0.3 v maximum junction temperature 150c operating temperature range ? 40 c to +125c storage temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may c ause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum ratin g conditions for extended periods may affect device reliability. esd caution
data s heet ad8479 rev. 0 | page 5 of 16 pin configuration and function descrip tions ref(?) 1 ?in 2 +in 3 4 nc 8 +v s ?v s 7 output 6 ref(+) 5 notes 1. nc = no connec t . do not connect t o this pin. ad8479 t op view (not to scale) 111 18-002 figure 3 . pin configuration table 3 . pin function descriptions pin no. mn emonic description 1 ref( ? ) ne gative reference voltage input. 2 ? in inverting input. 3 +in noninverting input. 4 ? v s negative supply voltage. 5 ref(+) positive refer ence voltage input. 6 output output. 7 +v s positive supply voltage. 8 nc no conne ct . do not connect to this pin.
ad8479 data sheet rev. 0 | page 6 of 16 typical performance characteristics v s = 15 v, t a = 25c, unless otherwise noted. ?150 ?100 ?50 0 50 100 0 10 20 30 40 50 60 cmrr (v/v) hits 11118-003 n = 393 mean = ?33.5249 sd = 30.5258 figure 4 . cmrr distribution ?300 ?200 0 ?100 100 200 300 0 10 20 30 40 50 70 60 gain error (v/v) hits 11118-004 n = 395 mean = ?29.0415 sd = 57.0658 figure 5 . gain error distribution ?4000 ?2000 0 2000 4000 0 10 20 30 40 50 70 60 offset vo lt age (v) hits 11118-005 n = 377 mean = 344.277 sd = 1086.57 figure 6 . offset voltage distribution 40 50 60 70 80 90 100 1 10 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) 111 18-006 figure 7 . cmrr vs. frequency 0 20 40 60 80 100 120 1 10 100 1k 10k 100k 1m psrr (db) frequency (hz) +psrr ?psrr 0.1 111 18-007 figure 8 . psrr vs. frequency 0 5 10 15 20 25 30 35 100 1k 10k 100k 1m v out (v p-p) frequenc y (hz) v s = 5 v v s = 1 5 v 111 18-008 figure 9 . large signal frequency response
data s heet ad8479 rev. 0 | page 7 of 16 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) 111 18-009 figure 10 . small signal frequency response ?800 ?600 ?400 ?200 0 200 400 600 800 ?20 ?15 ?10 ?5 0 5 10 15 20 common-mode vo lt age (v) v out (v) v s = 15 v v s = 5 v 111 18- 1 10 f igure 11 . input c ommon - m ode voltage vs. output voltage, dual supplies, v s = 15 v, 5 v 250 200 150 100 50 0 ?50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common-mode vo lt age (v) v out (v) v s = + 5v , v ref = 0v 111 18- 11 1 f igure 12 . input c ommon - m ode voltage vs. output voltage, sin gle supply, v s = + 5 v, v ref = 0 v ?100 ?50 0 50 100 150 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common-mode vo lt age (v) v out (v) v s = + 5v , v ref = m i ds upp l y 111 18- 1 12 f igure 13 . input c ommon - m ode voltage vs. output voltage, single supply, v s = +5 v, v ref = midsupply 11118-113 time (10s/div) 0.002%/div 5v/div 11.0s to 0.01% 15.4s to 0.001% figure 14 . settling time 11118-114 time (s) v out (v) ?8 ?4 20 15 10 5 0 ?5 ?10 ?15 ?20 0 4 8 12 16 20 24 28 32 r l = 2k? c l = 1000pf figure 15 . large signal pulse response
ad8479 data sheet rev. 0 | page 8 of 16 ?15 ?10 ?5 0 5 10 15 100 1k 10k 100k 1m v out (v) resis t ance (?) ?40c +2 5 c +8 5 c +1 0 5c +1 2 5c 111 18-014 figure 16 . output voltage vs. load over temperature ?15 ?10 ?5 0 5 10 15 0 5 10 15 20 25 30 35 40 45 v out (v) i load (ma) ?40c +2 5 c +8 5 c +1 0 5c +1 2 5c 111 18-015 figure 17 . output voltage vs . output current over temperature ?30 ?20 ?10 0 10 20 30 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 cmrr (v/v) temperature (c) normalized at 25c representative data 111 18- 1 17 figure 18 . cmrr vs. temper ature, v cm = 20 v ?100 ?50 0 50 100 150 200 ?40 111 18- 1 18 ?25 ?10 5 20 35 50 65 80 95 1 10 125 gain error (v/v) temper a ture (c) fi gure 19 . gain drift ?20 ?15 ?10 ?5 0 5 10 15 20 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearit y (ppm) v out (v) 111 18-019 figure 20 . gain nonlinearity ?8 ?6 ?4 ?2 0 2 4 6 8 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 output error (mv) v out (v) v s = 18v v s = 15v v s = 12v v s = 10v v s = 5v 111 18-020 normalized at 0v; offset to show different power supplies figure 21 . output error vs. output voltage, r l = 10 k ?
data s heet ad8479 rev. 0 | page 9 of 16 ?8 ?6 ?4 ?2 0 2 4 6 8 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 output error (mv) v out (v) v s = 18v v s = 15v v s = 12v v s = 10v v s = 5v 111 18-021 normalized at 0v; offset to show different power supplies figure 22 . output error vs. output voltage, r l = 2 k ? ?8 ?6 ?4 ?2 0 2 4 6 8 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 output error (mv) v out (v) v s = 18v v s = 15v v s = 12v v s = 10v v s = 5v 111 18-022 normalized at 0v; offset to show different power supplies figure 23 . output error vs. output voltage, r l = 1 k ? ?1 0 1 2 3 4 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 output error (mv) v out (v) r l = 10k? v s = 5v 111 18-023 r l = 2k? r l = 1k? figure 24 . output error vs. output voltage, v s = 5 v ?6 ?4 ?2 0 2 4 6 ?10 ?5 0 5 10 15 20 25 30 35 40 v out (mv) time (s) 111 18-025 f igure 25 . small signal pulse response ?6 ?4 ?2 0 2 4 6 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 v out (mv) time (s) c l = 1 . 47n f c l = 1 . 2 0n f c l = 1 . 67n f c l = 470p f c l = 1 .00 n f c l = 670p f 111 18-026 figure 26 . small signal pulse response vs. c ap acitive l oad ?60 ?40 ?20 0 20 40 60 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 shor t -circuit current (ma) temper a ture (c) ?i s c + i s c 111 18-027 figure 27 . short - c ircuit current vs. temperature
ad8479 data sheet rev. 0 | page 10 of 16 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 slew r a te (v/s) temper a ture (c) + sr ?sr 111 18-028 figure 28 . slew rate vs. temperature 400 420 440 460 480 500 520 540 560 580 600 2 4 6 8 10 12 14 16 18 supp l y current (a) supp l y vo lt age (v) 111 18-029 figure 29 . supply current vs. supply voltage 111 18-030 0 100 200 300 400 500 600 700 800 900 1000 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 supp l y current (a) temper a ture (c) v s = 1 5 v v s = 1 2 v v s = 5 v figure 30 . supply current vs. temperature 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 1 10 100 1k 10k 100k volt age noise spectra l densit y (v/hz) frequenc y (hz) v s = 15 v 111 18-031 figure 31 . voltage noise spectral density v s. frequency noise (20v/div) time (1s/div) 111 18-032 figure 32 . 0.1 hz to 10 hz noise
data s heet ad8479 rev. 0 | page 11 of 16 theory of o peration the ad8479 is a unity - gain, differen tial - to - single - ended amplifier that can reject extr emely high common - mode signals in excess of 600 v with 15 v supplies. the ad8479 consists of an operational amplifier (op amp) and a resistor network (see figure 33) . 2 3 4 1 7 6 8 ref(?) ?in 1m? ad8479 1m? +in ?v s nc +v s output 111 18-033 5 ref(+) notes 1. nc = no connec t . do not connect t o this pin. figure 33 . functional block diagram to achieve the high common - mode voltage range , an internal resistor divider connected to pin 3 and pin 5 attenuates the noninverting signal by a factor of 60. the internal resistors at pin 1 and pin 2, as well as the feedback resistor , restore the gain to provid e a differential gain of unity. the complete transfer function is v out = v (+in) ? v (?in) laser wafer - trimming provides resistor matching so that common - mode signals are rejected and differential input signals are amplified. to reduce output voltage drift, the op amp uses super beta tran - sistors in its input stage. the input offset cu rrent and its associated temperature coefficient contribute no appreciable output voltage offset or drift, which has the added benefit of reducing voltage noise because the corner where 1/f noise becomes dominant is below 5 hz. to reduce the dependence of gain accuracy on the op amp, the open - loop voltage gain of the op amp exceeds 20 million v/v , and the psrr exceeds 9 0 db .
ad8479 data sheet rev. 0 | page 12 of 16 applications information basic connections figure 34 shows the basic connections for operating the ad8479 with a dual supply. a supply voltage from 2.5 v to 18 v is applied across pin 7 and pin 4. both supplies should be decoupled close to the pins using 0.1 f capacitors. electrolytic capacitors of 10 f, also located close to the supply pins, may be required if low frequency noise is present on the power supply. although multiple amplifiers can be decoupled by a single set of 10 f capacitors, each ad8479 should have its own set of 0.1 f capacitors so that the decoupling point can be located directly at the ic power pins. ref(?) ref(+) ?v s ?v s + v s +v s v out = i shunt r shunt nc ?in +in r shunt i shunt (see text) (see text) 0.1f 0.1f +2.5v to +18v ?2.5v to ?18v nc = no connect ad8479 1 2 3 4 8 7 6 5 11118-034 figure 34. basic connections the differential input signal, which typically results from a load current flowing through a small shunt resistor, is applied to pin 2 and pin 3 with the polarity shown in figure 34 to obtain a positive gain. the common-mode voltage on the differential input signal can range from ?600 v to +600 v, and the maximum differential voltage is 14.7 v. when configured as shown in figure 34, the device operates as a simple gain-of-1, differential- to-single-ended amplifier; the output voltage is the shunt resistance times the shunt current. the output is measured with respect to pin 1 and pin 5. pin 1 and pin 5 (ref(?) and (ref(+)) should be grounded for a gain of unity and should be connected to the same low impedance ground plane. failure to do this results in degraded common-mode rejection. pin 8 is a no connect pin and should be left open. single-supply operation figure 35 shows the connections for operating the ad8479 with a single supply. because the output can swing to within only about 0.3 v of either rail, an offset must be applied to the output. this offset can be applied by connecting ref(+) and ref(?) to a low impedance reference voltage that is capable of sinking current (some adcs provide this voltage as an output). therefore, for a single supply of 10 v, v ref can be set to 5 v for a bipolar input signal, allowing the output to swing 9.4 v around the central 5 v reference voltage. for unipolar input signals, v ref can be set to approximately 1 v, allowing the output to swing from 1 v (for a 0 v input) to within 0.3 v of the positive rail. ref(?) ref(+) ?v s v y v x +v s +v s nc ?in +in r shunt i shunt 0.1f nc = no connect ad8479 1 2 3 4 8 7 6 5 output = v out ? v ref v ref 11118-035 figure 35. operation with a single supply when the ad8479 is operated with a single supply and a reference voltage is applied to ref(+) and ref(?), the input common-mode voltage range of the ad8479 is reduced. the reduced input common-mode range depends on the voltage at the inverting and noninverting inputs of the internal op amp, labeled v x and v y in figure 35. these nodes can swing to within 1 v of either rail. therefore, for a single supply voltage of 10 v, v x and v y can have a value from 1 v to 9 v. if v ref is set to 5 v, the allowable common-mode voltage range is +245 v to ?235 v. the common-mode voltage range can be calculated as follows: v cm () = 60 ( v x or v y ()) ? (59 v ref ) system-level decoupling and grounding the use of ground planes is recommended to minimize the impedance of ground returns and, therefore, the size of dc errors. figure 36 shows how to use grounding in a mixed-signal environ- ment, that is, with digital and analog signals present. to isolate low level analog signals from a noisy digital environment, many data acquisition components have separate analog and digital ground returns. all ground pins from mixed-signal components, such as adcs, should return through a low impedance analog ground plane. digital ground lines of mixed-signal converters should also be connected to the analog ground plane. analog power supply digital power supply 0.1f 0.1f 0.1f 0.1f +in ?in ?v s v in1 v in2 v dd v dd output agnd gnd microprocessor dgnd +v s ad8479 adc ref(?) ref(+) 7 4 3 2 6 1 5 12 +5v gnd +5v gnd ?5v 11118-036 figure 36. optimal grounding practice for a dual supply environment with separate analog and digital supplies
data sheet ad8479 rev. 0 | page 13 of 16 typically, analog and digital grounds should be separated. at the same time, however, the voltage difference between digital and analog grounds on a converter must also be minimized to keep this difference as small as possible (typically <0.3 v). the increased noisecaused by the digital return currents of the converter flowing through the analog ground planeis typically negligible. maximum isolation between analog and digital signals is achieved by connecting the ground planes back to the supplies. note that figure 36 suggests a star ground system for the analog circuitry, with all ground lines connected, in this case, to the analog ground of the adc. however, when ground planes are used, it is sufficient to connect ground pins to the nearest point on the low impedance ground plane. if only one power supply is available, it must be shared by both digital and analog circuitry. figure 37 shows how to minimize interference between the digital and analog circuitry. in figure 37, the reference of the adc is used to drive the ref(+) and ref(?) pins of the ad8479 . this means that the reference must be capable of sourcing and sinking a current equal to v cm /500 k. power supply v in1 v in2 v dd agnd dgnd adc 0.1f 0.1f +in ?in +v s output ?v s ad8479 ref(?) ref(+) v ref 4 7 3 2 6 1 5 v dd gnd microprocessor +5v gnd 0.1f 11118-037 figure 37. optimal grounding practice for a single-supply environment as in the dual-supply environment, separate analog and digital ground planes should be used (although reasonably thick traces can be used as an alternative to a digital ground plane). these ground planes should connect at the ground pin of the power supply. separate traces (or power planes) should run from the power supply to the supply pins of the digital and analog circuits. ideally, each device should have its own power supply trace, but these traces can be shared by a number of devices, as long as a single trace is not used to route current to both digital and analog circuitry. using a large shunt resistor the insertion of a large value shunt resistor across the input pins, pin 2 and pin 3, unbalances the input resistor network, thereby introducing common-mode error. the magnitude of the error depends on the common-mode voltage and the magnitude of the shunt resistor (r shunt ). table 4 shows some sample error voltages generated by a common-mode voltage of 600 v dc with shunt resistors from 20 to 2000 . assuming that the shunt resistor is selected to use the full 10 v output swing of the ad8479 , the error voltage becomes quite significant as the value of r shunt increases. table 4. error resulting from large values of r shunt (uncompensated circuit) r shunt () error v out (v) error indicated (ma) 20 0.012 0.6 1000 0.583 0.6 2000 1.164 0.6 to measure low current or current near zero in a high common- mode voltage environment, an external resistor equal to the shunt resistor value can be added to the low impedance side of the shunt resistor, as shown in figure 38. ref(?) ref(+) ?v s ?v s +v s +v s v out nc ?in +in r shunt r comp i shunt 0.1f 0.1f nc = no connect ad8479 1 2 3 4 8 7 6 5 11118-038 figure 38. compensating for large shunt resistors
ad8479 data sheet rev. 0 | page 14 of 16 o utput filtering to limit noise at the output, a simple two - pole, low - pass butter - worth filter can be implemented using the ada4077 - 2 after the ad8479 , as shown in figure 39 . ref(?) ref(+) ?v s ?v s +v s +v s +v s v out nc ?in +in 0.1f 0.1f 0.1f 0.1f nc = no connect ad8479 1 2 3 4 8 7 6 5 r1 r2 c2 ada4077-2 c1 111 18-039 figure 39 . filtering output noise using a two - pole butterworth filter table 5 provides recommended component values for various corner frequencies, along with the peak - to - p eak output noise for each case. gain of 60 diff erential a mplifier l ow level signals can be connected directly to the ?in and +in inputs of the ad8479 . d ifferential input signals can also be con - nected to give a precise gain of 60 (see figure 40 ); however, large common - mode voltages are no longer permissible. cold junction compensation can be implemented using a temperature sensor, such as the ad590 . ref(?) ref(+) +v s +v s nc ?in +in 0.1f nc = no connect ad8479 1 2 3 4 8 7 6 5 v out v ref thermocouple 111 18-041 figure 40 . gain of 60 thermocouple amplifier table 5. recommended values for two - pole butterworth filter corner frequency r1 r2 c1 c2 output noise (p - p) 50 khz 2.94 k ? 1% 1 . 58 k ? 1% 2.2 nf 10% 1 nf 10% 2.9 mv 5 khz 2.94 k ? 1% 1.58 k ? 1% 22 nf 10% 10 nf 10% 0 .9 mv 500 hz 2.94 k ? 1% 1.58 k ? 1% 220 nf 10% 0.1 f 10% 0.296 mv 50 hz 2.7 k ? 1 0% 1.58 k ? 1 0% 2.2 f 20% 0.1 f 20% 0.095 mv no filter 4.7 mv
data sheet ad8479 rev. 0 | page 15 of 16 error budget analysis example in the dc application described in this section, the 10 a output current from a device with a high common-mode voltage (such as a power supply or current-mode amplifier) is sensed across a 1 shunt resistor (see figure 41). the common-mode voltage is 600 v, and the resistor terminals are connected through a long pair of lead wires located in a high noise environment, for example, 50 hz/60 hz, 440 v ac power lines. the calculations in table 6 assume an induced noise level of 1 v p-p at 60 hz on the lead wires, in addition to a full-scale dc differential voltage of 10 v. the error budget table quantifies the contribution of each error source. note that the dominant error source in this example is due to the dc common-mode voltage. ref(?) output current 60hz power line 1 ? shunt ref(+) ?v s +v s v out nc ?in +in 0.1f 0.1f nc = no connect ad8479 1 2 3 4 8 7 6 5 10a 600v cm dc to ground 11118-042 figure 41. error budget analysis example: v in = 10 v full scale, v cm = 600 v dc, r shunt = 1 , 1 v p-p, 60 hz power line interference table 6. error budget analysis example (v cm = 600 v dc) error source calculation of error error (ppm of fs) accuracy, t a = 25c initial gain error (0.0001 10)/10 v 10 6 100 offset voltage (0.001 v/10 v) 10 6 100 dc cmr (over temperature) (32 10 ?6 600 v)/10 v 10 6 1920 total accuracy error 2120 temperature drift (85c) gain drift 5 ppm/c 60c 300 offset voltage drift (10 v/c 60c) 10 6 /10 v 60 total temperature drift error 360 resolution noise, typical, 0.01 hz to 10 hz, v p-p 35 v/10 v 10 6 4 cmr, 60 hz (32 10 ?6 1 v)/10 v 10 6 3 nonlinearity (5 10 ?6 10 v)/10 v 10 6 5 total resolution error 12 total error 2492
ad8479 data sheet rev. 0 | page 16 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off milli meter equiv alent s for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-012-aa 012407 -a 0.25 (0.0098) 0.17 (0.0 067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) sea ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.19 68) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.02 01) 0.31 (0.01 22) coplanarity 0.10 figure 42 . 8 - lead standard small outline package [ soic_n] narrow body (r - 8 ) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option ad8479arz ?40c to +1 2 5c 8- lead soic_n r -8 ad8479arz - rl ?40c to +1 2 5c 8 - lead soic_n, 13 - inch tape and reel, 2,500 pieces r - 8 ad8479brz ?40c to +1 2 5c 8- lead soic_n r -8 ad8479brz -rl ?40c to +1 2 5c 8- lead soic_n, 13- inch tape and reel, 2,500 pieces r -8 1 z = rohs compliant part. ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11118 - 0 - 4/13(0)

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